Analog Devices HSC-ADC-EVALC Manuale Utente

High Speed Converter Evaluation Platform HSC-ADC-EVALC Rev. 0 Evaluation boards are only intended for device evaluation and not for production purp

HSC-ADC-EVALC Rev. 0 | Page 10 of 32 06676-006SRAM ADDRESS AND CONTROLFPGA CONTROLSU21NC7SZ05M5XR1100ΩR403.74KΩR443.74KΩR423.74KΩR413.74KΩR433.74KΩ

HSC-ADC-EVALC Rev. 0 | Page 11 of 32 FPGA TO SRAM DATAXC4VFX20-10FFG672C06676-007XC4VFX20-10FFG672C Figure 7.

HSC-ADC-EVALC Rev. 0 | Page 12 of 32 AD19 TOBE USED WITH HIGHERDENSITY SRAM DEVICES06676-008 Figure 8.

HSC-ADC-EVALC Rev. 0 | Page 13 of 32 SRAM AND FPGA POWER06676-009XC4VFX20-10FFG672CXC4VFX20-10FFG672CR66499ΩR64499ΩR65499ΩR63499Ω Figure 9.

HSC-ADC-EVALC Rev. 0 | Page 14 of 32 06676-010REFCLK Oscillator for IDELAYCTRLFPGA BYPASS CAPSRAM A BYPASS CAPSRAM B BYPASS CAP++++R1524Ω Figure 10

HSC-ADC-EVALC Rev. 0 | Page 15 of 32 06676-011DEBUG PINSUNUSED ROCKET I/0 CONNECTIONSXC4VFX20-10FFG672CXC4VFX20-10FFG672C Figure 11.

HSC-ADC-EVALC Rev. 0 | Page 16 of 32 06676-012ROCKET I/0 CONNECTIONS Figure 12.

HSC-ADC-EVALC Rev. 0 | Page 17 of 32 06676-013USB CONNECTIONSR493.74ΩR713.74ΩR48100KΩSDI & SDO DIRECTIONS ARE WITHRESPECT TO THE DEVICE UNDERCO

HSC-ADC-EVALC Rev. 0 | Page 18 of 32 USB CONNECTIONS (CONTINUED)06676-014452136R523.74KΩR723.74KΩR46499ΩXC4VFX20-10FFG672CXC4VFX20-10FFG672CJ6 Figu

HSC-ADC-EVALC Rev. 0 | Page 19 of 32 06676-015EZ–KIT EXPANSION INTERFACE – FOR DSPsP1 P2 P3 Figure 15.

HSC-ADC-EVALC Rev. 0 | Page 2 of 32 TABLE OF CONTENTS Features ...

HSC-ADC-EVALC Rev. 0 | Page 20 of 32 ,06676-016TYCO HM – Zd CONNECTORSJ1HS-SERIAL/SPI/AUXJ2DATA BUS 1J3DATA BUS 2 Figure 16.

HSC-ADC-EVALC Rev. 0 | Page 21 of 32 06676-017CONFIGURATION EEPROMJTAG CONNECTOR EEPROM HARDWARERECONFIGURATIONPUSHBUTTONR573.74KΩR73ZEROR77100ΩR78

HSC-ADC-EVALC Rev. 0 | Page 22 of 32 POWER AND VOLTAGE REGULATORS06676-018+++++++++TSW–102–08–G–DDO NOTREMOVER68147k Figure 18.

HSC-ADC-EVALC Rev. 0 | Page 23 of 32 PCB LAYOUT 06676-019GENERAL PURPOSE I/O,USB/SPI CONTROL DATA BUS 1 DATA BUS 2XILINXVIRTEX-4FPGADEBUGPINSEXTERN

HSC-ADC-EVALC Rev. 0 | Page 24 of 32 I/O CONNECTOR—J1, J2, AND J3 PIN MAPPING DCBADCBADCBAD17A– D16A– D14A– D12A– D10A– D8A– D6A– D4A– D2A– D0A–D17

HSC-ADC-EVALC Rev. 0 | Page 25 of 32 DCBADCBAMGTCLK1– SD1– SD2– SD3– SD4– SD5– SD6– SD7– SD8– MGTCLK2–MGTCLK1+ SD1+ SD2+ SD3+ SD4+ SD5+ SD6+ SD7+ S

HSC-ADC-EVALC Rev. 0 | Page 26 of 32 Table 3. HSC-ADC-EVALC J1 I/O Connections to FPGA (U1) Connector J1 (HS-Serial, SPI, AUX) Schematic Net Name

HSC-ADC-EVALC Rev. 0 | Page 27 of 32 Table 5. HSC-ADC-EVALC J3 I/O Connections to FPGA (U1) Connector J3 (DATA BUS 2) Schematic Net Name FPGA Pin

HSC-ADC-EVALC Rev. 0 | Page 28 of 32 ORDERING INFORMATION BILL OF MATERIALS (RoHS COMPLIANT) Table 6. Qty Reference Designator Description Manufa

HSC-ADC-EVALC Rev. 0 | Page 29 of 32 Qty Reference Designator Description Manufacturer Part Number 17 L3 to L19 Ferrite chip, 220 Ω, 2 A, 0603,

HSC-ADC-EVALC Rev. 0 | Page 3 of 32 PRODUCT DESCRIPTION The Analog Devices, Inc. high speed converter evaluation platform (HSC-ADC-EVALC) includes

HSC-ADC-EVALC Rev. 0 | Page 30 of 32 Qty Reference Designator Description Manufacturer Part Number 2 U6, U7 IC, P-channel enhancement mode field

HSC-ADC-EVALC Rev. 0 | Page 31 of 32 NOTES

HSC-ADC-EVALC Rev. 0 | Page 32 of 32 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the pro

HSC-ADC-EVALC Rev. 0 | Page 4 of 32 EVALUATION BOARD HARDWAREHSC-ADC-EVALC ADC CAPTURE BOARD EASY START Requirements • HSC-ADC-EVALC ADC capture

HSC-ADC-EVALC Rev. 0 | Page 5 of 32 ROHDE & SCHWARZ,SMHU,2V p-p SIGNALSYNTHESIZERROHDE & SCHWARZ,SMHU,2V p-p SIGNALSYNTHESIZERBAND-PASSFILT

HSC-ADC-EVALC Rev. 0 | Page 6 of 32 HSC-ADC-EVALC ADC CAPTURE BOARD FEATURES 06676-002GENERAL PURPOSE I/O,USB/SPI CONTROL DATA BUS 1 DATA BUS 2FPGA

HSC-ADC-EVALC Rev. 0 | Page 7 of 32 06676-003 Figure 4. HSC-ADC-EVALC Components (Bottom View) HSC-ADC-EVALC SUPPORTED ADC EVALUATION BOARDS Refer

HSC-ADC-EVALC Rev. 0 | Page 8 of 32 THEORY OF OPERATION The HSC-ADC-EVALC evaluation platform is based around the Virtex-4 FPGA (XC4VFX20-10FFG672

HSC-ADC-EVALC Rev. 0 | Page 9 of 32 EVALUATION BOARD SCHEMATICS AND ARTWORK HSC-ADC-EVALC SCHEMATICS 06676-005TYCO AND DSP EZ–KIT CONNECTOR TO FP